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@rNAs destination operand being treated as ‘0(rn)’
0(rN)As source operand being treated as ‘@rn’
jCOND +NSkips next N bytes followed by jump instruction and equivalent to ‘jCOND $+N+2’
Also, there are some instructions, which cannot be found in other assemblers. These are branch instructions, which has different opcodes upon jump distance. They all got PC relative addressing mode.
beq labelA polymorph instruction which is ‘jeq label’ in case if jump distance within allowed range for cpu’s jump instruction. If not, this unrolls into a sequence of
jne $+6 br label
bne labelA polymorph instruction which is ‘jne label’ or ‘jeq +4; br label’
blt labelA polymorph instruction which is ‘jl label’ or ‘jge +4; br label’
bltn labelA polymorph instruction which is ‘jn label’ or ‘jn +2; jmp +4; br label’
bltu labelA polymorph instruction which is ‘jlo label’ or ‘jhs +2; br label’
bge labelA polymorph instruction which is ‘jge label’ or ‘jl +4; br label’
bgeu labelA polymorph instruction which is ‘jhs label’ or ‘jlo +4; br label’
bgt labelA polymorph instruction which is ‘jeq +2; jge label’ or ‘jeq +6; jl +4; br label’
bgtu labelA polymorph instruction which is ‘jeq +2; jhs label’ or ‘jeq +6; jlo +4; br label’
bleu labelA polymorph instruction which is ‘jeq label; jlo label’ or ‘jeq +2; jhs +4; br label’
ble labelA polymorph instruction which is ‘jeq label; jl label’ or ‘jeq +2; jge +4; br label’
jump labelA polymorph instruction which is ‘jmp label’ or ‘br label’
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